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Manufacturing and Test Considerations in System-On-Chip Designs
Calcutta, India January 04-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.81260513th International Conference on VLSI ...
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M. d'Abreu, "Manufacturing and Test Considerations in System-On-Chip Designs," VLSI Design, International Conference on, pp. 176, 13th International Conference on VLSI Design, 2000.
 
 
BibTex
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@article{ 10.1109/ICVD.2000.812605,
author = {M. d'Abreu},
title = {Manufacturing and Test Considerations in System-On-Chip Designs},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2000},
issn = {1063-9667},
pages = {176},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812605},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Manufacturing and Test Considerations in System-On-Chip Designs
SN - 1063-9667
SP
EP
A1 - M. d'Abreu,
PY - 2000
VL - 0
JA - VLSI Design, International Conference on
ER -
 
M. d'Abreu, Level One Communications Inc.
This session describes the impact of cost at four stages in the design cycle - (a) architecture (b) synthesis and (c) layout and (d) test. This will be done using data from example industrial SoC. In addition, methodologies to reduce costs at each of these three stages will be proposed.
Citation:
M. d'Abreu, "Manufacturing and Test Considerations in System-On-Chip Designs," vlsid, pp.176, 13th International Conference on VLSI Design, 2000
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