This paper presents a case for next generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect yield model, which estimates yield as a function of net list attributes. Testability oriented synthesis encompasses various Design-for-Test (DFT), Synthesis for Testability (SFT) and the High-Level Test Synthesis (HLTS) techniques during the synthesis process.