Dataflow Analysis for Resource Contention and Register Leakage Properties

Calcutta, India January 04-January 07

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http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812643

13th International Conference on VLSI ...

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	ASCII Text	x
	Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata, "Dataflow Analysis for Resource Contention and Register Leakage Properties," VLSI Design, International Conference on, pp. 418, 13th International Conference on VLSI Design, 2000.

	BibTex	x
	@article{ 10.1109/ICVD.2000.812643, author = {Subir K. Roy and Hiroaki Iwashita and Tsuneo Nakata}, title = {Dataflow Analysis for Resource Contention and Register Leakage Properties}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2000}, issn = {1063-9667}, pages = {418}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812643}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Dataflow Analysis for Resource Contention and Register Leakage Properties SN - 1063-9667 SP EP A1 - Subir K. Roy, A1 - Hiroaki Iwashita, A1 - Tsuneo Nakata, PY - 2000 KW - Resource Contention KW - Register Leakage KW - Formal Verification KW - Simulation VL - 0 JA - VLSI Design, International Conference on ER -

Subir K. Roy, Fujitsu Laboratories Limited

Hiroaki Iwashita, Fujitsu Laboratories Limited

Tsuneo Nakata, Fujitsu Laboratories Limited

Resource contention and register leakage are two important classes of properties which need to be verified in every design to identify difficult bugs. They can be derived automatically from the RTL implementation model. In this paper, an approach for their systematic formulation is given. The automated approach unburdens the verification team from the tedious process of formulating them, thereby, allowing focus on the formulation of other important properties.

Index Terms:

Resource Contention, Register Leakage, Formal Verification, Simulation

Citation:

Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata, "Dataflow Analysis for Resource Contention and Register Leakage Properties," vlsid, pp.418, 13th International Conference on VLSI Design, 2000

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