loading...
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
Bangalore, India January 03-January 07
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902686The 14th International Conference on ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Nagaraj Ns, Poras Balsara, Cyrus Cantrell, "Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations," VLSI Design, International Conference on, pp. 365, The 14th International Conference on VLSI Design (VLSID '01), 2001.
 
 
BibTex
x
 
@article{ 10.1109/ICVD.2001.902686,
author = {Nagaraj Ns and Poras Balsara and Cyrus Cantrell},
title = {Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2001},
issn = {1063-9667},
pages = {365},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902686},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
SN - 1063-9667
SP
EP
A1 - Nagaraj Ns,
A1 - Poras Balsara,
A1 - Cyrus Cantrell,
PY - 2001
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Nagaraj Ns, Texas Instruments Inc.
Poras Balsara, University of Texas at Dallas
Cyrus Cantrell, University of Texas at Dallas
Interconnect parasitics are playing a significant role in design and analysis in deep sub-micron (DSM) technologies. Interconnect process variations could play a significant role in achieving predictable yield. Crosstalk noise is one of the increasingly important careabouts in DSM designs. In this paper, a practical method to analyze the crosstalk noise effects with interconnect process variations using corner-based approach is described. The results from application of this method on a large DSP design implemented in 0.18u technology is presented. Application of the proposed method resulted in detection of a new worstcase interconnect process corner that was not included in the design methodology.
Citation:
Nagaraj Ns, Poras Balsara, Cyrus Cantrell, "Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations," vlsid, pp.365, The 14th International Conference on VLSI Design (VLSID '01), 2001
Usage of this product signifies your acceptance of the Terms of Use.