An On-Chip Coupling Capacitance Measurement Technique

Bangalore, India January 03-January 07

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http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902707

The 14th International Conference on ...

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	Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai, "An On-Chip Coupling Capacitance Measurement Technique," VLSI Design, International Conference on, pp. 495, The 14th International Conference on VLSI Design (VLSID '01), 2001.

	BibTex	x
	@article{ 10.1109/ICVD.2001.902707, author = {Pratheep A. Nair and Anubhav Gupta and Madhav P. Desai}, title = {An On-Chip Coupling Capacitance Measurement Technique}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2001}, issn = {1063-9667}, pages = {495}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902707}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - An On-Chip Coupling Capacitance Measurement Technique SN - 1063-9667 SP EP A1 - Pratheep A. Nair, A1 - Anubhav Gupta, A1 - Madhav P. Desai, PY - 2001 VL - 0 JA - VLSI Design, International Conference on ER -

Pratheep A. Nair, Indian Institute of Technology

Anubhav Gupta, Indian Institute of Technology

Madhav P. Desai, Indian Institute of Technology

We describe a technique for the accurate measurement of on-chip coupling capacitance using a Charge Based Coupling Capacitance Measurement (CBCCM) Technique. Detailed circuit simulations show that this method can measure subfemtofarad coupling capacitance values, and can be used to isolate and measure components of device capacitance as well.

Citation:

Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai, "An On-Chip Coupling Capacitance Measurement Technique," vlsid, pp.495, The 14th International Conference on VLSI Design (VLSID '01), 2001

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