To address the problem of accurate timing characterization, in this paper, we take the mode dependent characterization approach further and apply the notion of the global false path, the functional delay analysis between modes to a previous timing analysis of circuits and propose a new timing characterization method. Our method is applied to ISCAS-85 benchmark circuits and an industrial IP block. Experimental results show that this method is able to generate timing models with very tight path delays that are guaranteed to give correct results, and the delays of the I/O paths between the control inputs and outputs can be calculated more accurately than the previous approaches, thereby significantly improving the accuracy of timing models.