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A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory
Saint Raphael, French Riviera, France July 06-July 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.1111th IEEE International On-Line Testi ...
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Andrzej Krasniewski, "A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 197-198, 11th IEEE International On-Line Testing Symposium, 2005.
 
 
BibTex
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@article{ 10.1109/IOLTS.2005.11,
author = {Andrzej Krasniewski},
title = {A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2005},
issn = {1530-1591},
pages = {197-198},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.11},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory
SN - 1530-1591
SP197
EP198
A1 - Andrzej Krasniewski,
PY - 2005
KW - null
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
Andrzej Krasniewski, Warsaw University of Technology
We present several low-cost concurrent error detection schemes for a sequential circuit implemented using FPGAs with embedded memory blocks. The experimental results show that for many of the examined circuits, a reasonable level of error detection can be obtained at the circuitry overhead of less than 10% - a level recommended by proponents of a "pragmatic" approach to on-line testing.
Citation:
Andrzej Krasniewski, "A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory," iolts, pp.197-198, 11th IEEE International On-Line Testing Symposium, 2005
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