As device geometries shrink, power supply voltage decreases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming crucial in determining the signal integrity of a system. In this paper we propose new ways of merging transition reducing coding techniques with coding techniques for fault tolerant busses (implementing either error detecting codes and error recovery, or correcting codes). In particular, we focus on merging bus-invert code along with the employed error detection or correction coding technique, and show that the maximum number of simultaneous switching drivers can be drastically reduced, thus reducing the SSN and increasing signal integrity. Furthermore, we show how, by properly merging the bus invert encoder and the check bit generator, the latency introduced by the proposed coding techniques can be minimized and the number of additional wires can be kept minimal.