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Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift
Saint Raphael, French Riviera, France July 06-July 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.2211th IEEE International On-Line Testi ...
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Kentaroh Katoh, Abderrahim Doumar, Hideo Ito, "Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 203-204, 11th IEEE International On-Line Testing Symposium, 2005.
 
 
BibTex
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@article{ 10.1109/IOLTS.2005.22,
author = {Kentaroh Katoh and Abderrahim Doumar and Hideo Ito},
title = {Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2005},
issn = {1530-1591},
pages = {203-204},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.22},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift
SN - 1530-1591
SP203
EP204
A1 - Kentaroh Katoh,
A1 - Abderrahim Doumar,
A1 - Hideo Ito,
PY - 2005
KW - null
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
Kentaroh Katoh, Chiba University
Abderrahim Doumar, Alakhawayn University
Hideo Ito, Chiba University
In this paper, a new design for online testing of System on a Chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which will keep its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.
Citation:
Kentaroh Katoh, Abderrahim Doumar, Hideo Ito, "Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift," iolts, pp.203-204, 11th IEEE International On-Line Testing Symposium, 2005
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