Efficient Estimation of SEU Effects in SRAM-Based FPGAs

Saint Raphael, French Riviera, France July 06-July 08

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.26

11th IEEE International On-Line Testi ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by M. Sonza Reorda Articles by L. Sterpone Articles by M. Violante

	ASCII Text	x
	M. Sonza Reorda, L. Sterpone, M. Violante, "Efficient Estimation of SEU Effects in SRAM-Based FPGAs," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 54-59, 11th IEEE International On-Line Testing Symposium, 2005.

	BibTex	x
	@article{ 10.1109/IOLTS.2005.26, author = {M. Sonza Reorda and L. Sterpone and M. Violante}, title = {Efficient Estimation of SEU Effects in SRAM-Based FPGAs}, journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2005}, issn = {1530-1591}, pages = {54-59}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.26}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International TI - Efficient Estimation of SEU Effects in SRAM-Based FPGAs SN - 1530-1591 SP54 EP59 A1 - M. Sonza Reorda, A1 - L. Sterpone, A1 - M. Violante, PY - 2005 KW - null VL - 0 JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International ER -

M. Sonza Reorda, Politecnico di Torino

L. Sterpone, Politecnico di Torino

M. Violante, Politecnico di Torino

SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to Single Event Upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs? configuration memory. In this paper we propose a new method for assessing the impact of faults in the configuration memory on the FPGA dependability. The method uses static analysis, thus reducing greatly the time for performing dependability evaluation.

Citation:

M. Sonza Reorda, L. Sterpone, M. Violante, "Efficient Estimation of SEU Effects in SRAM-Based FPGAs," iolts, pp.54-59, 11th IEEE International On-Line Testing Symposium, 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.