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Hardening Techniques against Transient Faults for Asynchronous Circuits
Saint Raphael, French Riviera, France July 06-July 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.3011th IEEE International On-Line Testi ...
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Y. Monnet, M. Renaudin, R. Leveugle, "Hardening Techniques against Transient Faults for Asynchronous Circuits," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 129-134, 11th IEEE International On-Line Testing Symposium, 2005.
 
 
BibTex
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@article{ 10.1109/IOLTS.2005.30,
author = {Y. Monnet and M. Renaudin and R. Leveugle},
title = {Hardening Techniques against Transient Faults for Asynchronous Circuits},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2005},
issn = {1530-1591},
pages = {129-134},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.30},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - Hardening Techniques against Transient Faults for Asynchronous Circuits
SN - 1530-1591
SP129
EP134
A1 - Y. Monnet,
A1 - M. Renaudin,
A1 - R. Leveugle,
PY - 2005
KW - null
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
Y. Monnet, TIMA laboratory
M. Renaudin, TIMA laboratory
R. Leveugle, TIMA laboratory
This paper presents hardening techniques against transient faults for Quasi Delay Insensitive (QDI) circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe consequences on the circuit behavior. Three techniques exploiting QDI circuit properties are proposed for hardening. These techniques improve the tolerance to transient faults, and make their detection easier. These techniques are compared in terms of efficiency and cost.
Citation:
Y. Monnet, M. Renaudin, R. Leveugle, "Hardening Techniques against Transient Faults for Asynchronous Circuits," iolts, pp.129-134, 11th IEEE International On-Line Testing Symposium, 2005
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