loading...
Impact of Soft Error Challenge on SoC Design
Saint Raphael, French Riviera, France July 06-July 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.3611th IEEE International On-Line Testi ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Y. Zorian, Virage Logic Corporation
V. A. Vardanian, Virage Logic Yerevan Branch
K. Aleksanyan, Virage Logic Yerevan Branch
K. Amirkhanyan, Virage Logic Yerevan Branch
Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today's nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design.
Citation:
Y. Zorian, V. A. Vardanian, K. Aleksanyan, K. Amirkhanyan, "Impact of Soft Error Challenge on SoC Design," iolts, pp.63-68, 11th IEEE International On-Line Testing Symposium, 2005
Usage of this product signifies your acceptance of the Terms of Use.