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Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM
Saint Raphael, French Riviera, France July 06-July 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2005.5911th IEEE International On-Line Testi ...
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Balkaran Gill, Case Western Reserve University
Michael Nicolaidis, IROC Technologies
Chris Papachristou, Case Western Reserve University
In this paper, we introduce an approach for Single-word Multiple-bit Upsets (SMU) correction in SRAM. This approach uses the combination of Built in Current Sensor (BICS) and Hamming Single Error Correction/Double Error Detection (SEC/DED) codes. The BICS is used with memory columns for online detection of upsets. When the upset is detected by the BICS, an immediate error correction is performed by the ECC. If ECC gives flag for uncorrectable error i.e. double or more errors in single word, then information from BICS is used to invert the data read from columns flagged by the BICS.
Citation:
Balkaran Gill, Michael Nicolaidis, Chris Papachristou, "Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM," iolts, pp.266-271, 11th IEEE International On-Line Testing Symposium, 2005
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