Systems on a chip (SoCs) that combine several processor cores plus multiple interconnects are becoming a standard in advanced technologies. For such systems, a comprehensive test strategy that combines external test and self test capabilities as well as on-line and off-line test is becoming a must in order to manage fault mechanisms that are expected for deep sub-micron technologies. Recently, we have developed a hierarchical test concept for SoCs that relies on a test processor as a "hard core". This paper describes an advanced test concept that may serve to support off-line self test as well as advanced on-line test, also including fault diagnosis features.