Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study

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http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.48

12th IEEE International On-Line Testi ...

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	Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel, "Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 165-172, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.

	BibTex	x
	@article{ 10.1109/IOLTS.2006.48, author = {Cristiano Lazzari and Ricardo A. L. Reis and Lorena Anghel}, title = {Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study}, journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International}, volume = {0}, year = {2006}, isbn = {0-7695-2620-9}, pages = {165-172}, doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.48}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International TI - Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study SN - 0-7695-2620-9 SP165 EP172 A1 - Cristiano Lazzari, A1 - Ricardo A. L. Reis, A1 - Lorena Anghel, PY - 2006 KW - null VL - 0 JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International ER -

Cristiano Lazzari, UFRGS, Brazil

Ricardo A. L. Reis, UFRGS, Brazil

Lorena Anghel, TIMA Laboratory, France

This paper reports a case study about the automatic layout generation and transient fault injection analysis of a Phase-Locked Loop (PLL). A script methodology was used to generate the layout based on transistor level specifications. After layout validation, experiences were performed in the PLL in order to evaluate the sensibility against transient fault. The circuit was generated using the STMicroelectronics HCMOS8D process (0.18?m). Results report the PLL sensitive points allowing the study and development of techniques to protect this circuit against transient faults.

Citation:

Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel, "Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study," iolts, pp.165-172, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006

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