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Should Logic SER be Solved at the Circuit Level?
Lake of Como, Italy July 10-July 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.5612th IEEE International On-Line Testi ...
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T. M. Mak, S. Mitra, "Should Logic SER be Solved at the Circuit Level?," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 199, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.
 
 
BibTex
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@article{ 10.1109/IOLTS.2006.56,
author = {T. M. Mak and S. Mitra},
title = {Should Logic SER be Solved at the Circuit Level?},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2006},
isbn = {0-7695-2620-9},
pages = {199},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.56},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - Should Logic SER be Solved at the Circuit Level?
SN - 0-7695-2620-9
SP
EP
A1 - T. M. Mak,
A1 - S. Mitra,
PY - 2006
KW - null
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
T. M. Mak, Intel Corporation
S. Mitra, Stanford University
SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also been some work at the process level (e.g., SOI), but recently, there is also some research work on circuit level (e.g., cell hardening, BISER), but there has not been a wide spread adoption yet. Can logic SER be solved at the circuit level? Should they be? We have a team of experts from system, architecture and circuit area to debate this topic.
Citation:
T. M. Mak, S. Mitra, "Should Logic SER be Solved at the Circuit Level?," iolts, pp.199, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006
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