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Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
Heraklion, Crete, Greece July 08-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.3313th IEEE International On-Line Testi ...
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Y. Monnet, M. Renaudin, R. Leveugle, "Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 113-120, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
 
 
BibTex
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@article{ 10.1109/IOLTS.2007.33,
author = {Y. Monnet and M. Renaudin and R. Leveugle},
title = {Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2007},
isbn = {0-7695-2918-6},
pages = {113-120},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.33},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
SN - 0-7695-2918-6
SP113
EP120
A1 - Y. Monnet,
A1 - M. Renaudin,
A1 - R. Leveugle,
PY - 2007
KW - null
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
Y. Monnet, TIMA Laboratory, France
M. Renaudin, TIMA Laboratory, France
R. Leveugle, TIMA Laboratory, France
Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of Quasi Delay Insensitive (QDI) asynchronous circuits in the presence of SEUs (memory bit flips). The circuits and the fault injection process are both described using this model. The method, based on symbolic simulation, consists of exploring all the reachable states in the presence of faults in order to draw up an exhaustive list of behaviors. A case study shows that this method enables us to verify some properties on the circuits. SEU resistance can be formally proven using this analysis.
Citation:
Y. Monnet, M. Renaudin, R. Leveugle, "Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs," iolts, pp.113-120, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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