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Fuse: A Technique to Anticipate Failures due to Degradation in ALUs
Heraklion, Crete, Greece July 08-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.3413th IEEE International On-Line Testi ...
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Jaume Abella, Intel Barcelona Research Center
Xavier Vera, Intel Barcelona Research Center
Osman Unsal, Intel Barcelona Research Center
Oguz Ergin, Intel Barcelona Research Center
Antonio Gonz?lez, Intel Barcelona Research Center
This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (Arithmetic Logic Unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.
Citation:
Jaume Abella, Xavier Vera, Osman Unsal, Oguz Ergin, Antonio Gonz?lez, "Fuse: A Technique to Anticipate Failures due to Degradation in ALUs," iolts, pp.15-22, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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