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Soft Errors: Technology Trends, System Effects, and Protection Techniques
Heraklion, Crete, Greece July 08-July 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.6113th IEEE International On-Line Testi ...
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Subhasish Mitra, Pia Sanda, Norbert Seifert, "Soft Errors: Technology Trends, System Effects, and Protection Techniques," IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International, pp. 4, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
 
 
BibTex
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@article{ 10.1109/IOLTS.2007.61,
author = {Subhasish Mitra and Pia Sanda and Norbert Seifert},
title = {Soft Errors: Technology Trends, System Effects, and Protection Techniques},
journal ={IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International},
volume = {0},
year = {2007},
isbn = {0-7695-2918-6},
pages = {4},
doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2007.61},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
TI - Soft Errors: Technology Trends, System Effects, and Protection Techniques
SN - 0-7695-2918-6
SP
EP
A1 - Subhasish Mitra,
A1 - Pia Sanda,
A1 - Norbert Seifert,
PY - 2007
KW - Soft errors
KW - Memory soft errors
KW - Logic soft errors
KW - Error Correcting Codes
KW - FITs
KW - timing derating
KW - logic derating
KW - architectural derating
KW - radiation hardening
KW - Built-In Soft Error Resilience
KW - error detection
KW - recovery
KW - data integrity
KW - reliability
KW - availability
VL - 0
JA - IEEE International On-Line Testing Symposium/On-Line Testing Symposium, IEEE International
ER -
 
Subhasish Mitra, Stanford University
Pia Sanda, IBM
Radiation-induced soft errors are getting worse in digital systems manufactured in advanced technologies. Stringent data integrity and availability requirements of enterprise computing and networking applications demand special attention to soft errors in sequential elements and combinational logic. This tutorial will discuss the impact of technology scaling on soft error rates, circuit-level modeling of soft errors, architectural impact of soft errors, challenges associated with evaluation of run-time behaviors of systems in the presence of soft errors, actual data on system behaviors in the presence of soft errors, metrics for quantifying soft error vulnerabilities, design of architectures with Built-in-Soft-Error-Resilience techniques, and actual case studies.
Index Terms:
Soft errors, Memory soft errors, Logic soft errors, Error Correcting Codes, FITs, timing derating, logic derating, architectural derating, radiation hardening, Built-In Soft Error Resilience, error detection, recovery, data integrity, reliability, availability
Citation:
Subhasish Mitra, Pia Sanda, Norbert Seifert, "Soft Errors: Technology Trends, System Effects, and Protection Techniques," iolts, pp.4, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
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