When designing a SoC, matching the required performance both in terms of processing power and power consumption tends to become more and more challenging. Moreover, since the range of targeted applications for every single product is growing rapidly, employing reconfigurable accelerators makes more and more sense to this purpose. Coarse grain reconfigurable architectures bring an alternative providing interesting performance / flexibility trade-offs over traditional approaches. This paper presents an original method allowing to efficiently exploit dynamical parallelism at both loop-level and task-level, which remains rarely used. This method called DHM (Dynamic Hardware Multiplexing) is based upon the use of a hardwired controller dedicated to run-time task scheduling and automatic loop unrolling. This paper shows that significant performance improvements can be achieved through combining both intra and inter-task parallelism. Principles and validations are exposed through a case study on a coarse grain reconfigurable architecture.