loading...
Experiences with Soft-Core Processor Design
Denver, Colorado April 04-April 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.20919th IEEE International Parallel and ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen D. Brown, "Experiences with Soft-Core Processor Design," Parallel and Distributed Processing Symposium, International, vol. 4, pp. 167b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005.
 
 
BibTex
x
 
@article{ 10.1109/IPDPS.2005.209,
author = {Franjo Plavec and Blair Fort and Zvonko G. Vranesic and Stephen D. Brown},
title = {Experiences with Soft-Core Processor Design},
journal ={Parallel and Distributed Processing Symposium, International},
volume = {4},
year = {2005},
issn = {1530-2075},
pages = {167b},
doi = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.209},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel and Distributed Processing Symposium, International
TI - Experiences with Soft-Core Processor Design
SN - 1530-2075
SP
EP
A1 - Franjo Plavec,
A1 - Blair Fort,
A1 - Zvonko G. Vranesic,
A1 - Stephen D. Brown,
PY - 2005
KW - null
VL - 4
JA - Parallel and Distributed Processing Symposium, International
ER -
 
Franjo Plavec, University of Toronto, Canada
Blair Fort, University of Toronto, Canada
Zvonko G. Vranesic, University of Toronto, Canada
Stephen D. Brown, University of Toronto, Canada
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera's Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.
Citation:
Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen D. Brown, "Experiences with Soft-Core Processor Design," ipdps, vol. 4, pp.167b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3, 2005
Usage of this product signifies your acceptance of the Terms of Use.