This paper proposes a new CLB architecture for FPGAs and associated online testing and reconfiguration techniques that detect configuration upsets in the LUTs of SRAMbased FPGAs and correct them using partial reconfiguration. These configuration upsets may either be Single Event Upsets(SEUs) or even Multiple Configuration Upsets. Any error in a CLB is detected with a latency of just 16 clock cycles and the erros are diagnosed by propagating them to a single output port by a chain-like shift register. The proposed CLB architectures requires only 2 additional SRAM configuration bits per LUT for a Xilinx Virtex II architecture. This is extremely low when compared to the 16 additional SRAM configuration bits required by CLB architectures used to implement standard DWC techniques for detecting configuration upsets in LUTs.