Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. When designing a system that includes this feature it has to be made sure, that no signal lines cross the border to other reconfigurable regions. The complex modular design flow to generate partial bitstreams and the need of macros for physical interconnection of IP-Cores causes the necessity to investigate in alternatives. This paper describes the design and implementation of a software reconfigurable multiprocessor system, based on Xilinx MicroBlaze softcore processors. A real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA is used to present results.