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An Architecture for Software-Based iSCSI on Multiprocessor Servers
Denver, Colorado April 04-April 08
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2005.8919th IEEE International Parallel and ...
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Annie Foong, Intel Corporation
Gary McAlpine, Intel Corporation
Dave Minturn, Intel Corporation
Greg Regnier, Intel Corporation
Vikram Saletore, Intel Corporation
To achieve IP-converged cluster deployments, the performance and scalability of iSCSI must approach that of FC SANs. We recognize and quantify that the major overhead of iSCSI comes from TCP/IP processing. Industry has largely responded with TCP offload engines (TOEs) and iSCSI storage adapters. As an alternative, this paper shows a software implementation of iSCSI on generic OSes and processors. The trend towards chip multiprocessing (CMP) and integrated memory controllers (MCH) largely motivated our direction. With CMP, increased processing power is delivered through multiple cores per processor; on-die MCH allows memory bandwidth to scale better with processor speeds. Our approach and analysis shows the effectiveness of partitioning the workload suitable for a CMP system, allowing iSCSI to scale with the increasing processing power and memory bandwidth of servers over time.
Citation:
Annie Foong, Gary McAlpine, Dave Minturn, Greg Regnier, Vikram Saletore, "An Architecture for Software-Based iSCSI on Multiprocessor Servers," ipdps, vol. 10, pp.213b, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 9, 2005
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