Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer

University of Calgary, Canada May 19-May 21

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http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.31

35th International Symposium on Multi ...

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	Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama, "Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer," Multiple-Valued Logic, IEEE International Symposium on, pp. 114-119, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005.

	BibTex	x
	@article{ 10.1109/ISMVL.2005.31, author = {Tomoaki Hasegawa and Yuya Homma and Michitaka Kameyama}, title = {Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2005}, issn = {0195-623X}, pages = {114-119}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2005.31}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer SN - 0195-623X SP114 EP119 A1 - Tomoaki Hasegawa, A1 - Yuya Homma, A1 - Michitaka Kameyama, PY - 2005 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Tomoaki Hasegawa, Tohoku University, Japan

Yuya Homma, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

A packet data transfer scheme is introduced for intrachip data transfer to solve an interconnection problem. A protocol suitable for intra-chip data transfer is proposed to make a router as simple as possible. The total number of packets in a micronetwork can be reduced by multiplexing two binary packets into a single multiple-valued packet, which makes the micronetwork throughput very high. The multiplexing can be realized by liner summation of two packets in current-mode logic. Moreover, multiple-valued source-coupled logic is introduced in the router circuit. Thus, we can design the very high-speed micronetwork using current-mode multiple-valued logic.

Citation:

Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama, "Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer," ismvl, pp.114-119, 35th International Symposium on Multiple-Valued Logic (ISMVL'05), 2005

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