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Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic
Singapore May 17-May 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.1036th International Symposium on Multi ...
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Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic," Multiple-Valued Logic, IEEE International Symposium on, pp. 2, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISMVL.2006.10,
author = {Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi},
title = {Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {0195-623X},
pages = {2},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.10},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic
SN - 0195-623X
SP
EP
A1 - Naofumi Homma,
A1 - Takafumi Aoki,
A1 - Tatsuo Higuchi,
PY - 2006
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Naofumi Homma, Tohoku University, Sendai, Japan
Takafumi Aoki, Tohoku University, Sendai, Japan
Tatsuo Higuchi, Tohoku Institute of Technology, Japan
This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to represent various addition algorithms for any positional number system. In this paper, we introduce an extension of CTDs for representing possible fast addition algorithms with redundant number systems. Using the extended version of CTDs, we can classify the conventional fast adder structures including those using emerging multiple-valued logic devices into three types in a systematic way.
Citation:
Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic," ismvl, pp.2, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006
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