Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals

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http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.40

36th International Symposium on Multi ...

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	Yoshihiro NAKATANI, Masanori HARIYAMA, Michitaka KAMEYAMA, "Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals," Multiple-Valued Logic, IEEE International Symposium on, pp. 17, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.

	BibTex	x
	@article{ 10.1109/ISMVL.2006.40, author = {Yoshihiro NAKATANI and Masanori HARIYAMA and Michitaka KAMEYAMA}, title = {Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {0195-623X}, pages = {17}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.40}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals SN - 0195-623X SP EP A1 - Yoshihiro NAKATANI, A1 - Masanori HARIYAMA, A1 - Michitaka KAMEYAMA, PY - 2006 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Yoshihiro NAKATANI, Graduate School of Information Sciences, Tohoku Univers, Japan

Masanori HARIYAMA, Graduate School of Information Sciences, Tohoku Univers, Japan

Michitaka KAMEYAMA, Graduate School of Information Sciences, Tohoku Univers, Japan

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Citation:

Yoshihiro NAKATANI, Masanori HARIYAMA, Michitaka KAMEYAMA, "Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals," ismvl, pp.17, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006

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