loading...
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors
Singapore May 17-May 20
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.636th International Symposium on Multi ...
 This Article 
 
Buy PURCHASE ARTICLE: $19
PDF
HTML
Buy IEEE Xplore Subscribers
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
ASCII Text
x 
 
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi, "A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors," Multiple-Valued Logic, IEEE International Symposium on, pp. 19, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.
 
 
BibTex
x
 
@article{ 10.1109/ISMVL.2006.6,
author = {Katsuhiko Degawa and Takafumi Aoki and Tatsuo Higuchi and Hiroshi Inokawa and Katsuhiko Nishiguchi and Yasuo Takahashi},
title = {A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors},
journal ={Multiple-Valued Logic, IEEE International Symposium on},
volume = {0},
year = {2006},
issn = {0195-623X},
pages = {19},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.6},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Multiple-Valued Logic, IEEE International Symposium on
TI - A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors
SN - 0195-623X
SP
EP
A1 - Katsuhiko Degawa,
A1 - Takafumi Aoki,
A1 - Tatsuo Higuchi,
A1 - Hiroshi Inokawa,
A1 - Katsuhiko Nishiguchi,
A1 - Yasuo Takahashi,
PY - 2006
KW - null
VL - 0
JA - Multiple-Valued Logic, IEEE International Symposium on
ER -
 
Katsuhiko Degawa, Tohoku University, Sendai 980-8579, Japan
Takafumi Aoki, Tohoku University, Sendai 980-8579, Japan
Tatsuo Higuchi, Tohoku Institute of Technology, Japan
Hiroshi Inokawa, NTT Corporation, Japan
Katsuhiko Nishiguchi, NTT Corporation, Japan
Yasuo Takahashi, Graduate School of Information Science and Technology, Hokkaido University, Japan
This paper presents a circuit design of a Ternary Content-Addressable Memory (TCAM) using Single- Electron Transistors (SETs). The proposed TCAM cell employs a SET-based ternary memory and a dual-gate SET for ternary data matching. The multi-level functionality of SET is fully utilized to reduce circuit complexity. Basic matching operation of the TCAM cell is verified using a multi-gate SET and a MOSFET fabricated on the same Silicon-On-Insulator (SOI) wafer by Pattern-Dependent OXidation (PADOX) process.
Citation:
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi, "A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors," ismvl, pp.19, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.