A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors

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http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.9

36th International Symposium on Multi ...

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	los Roberto Junior Mingoto, "A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors," Multiple-Valued Logic, IEEE International Symposium on, pp. 15, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006.

	BibTex	x
	@article{ 10.1109/ISMVL.2006.9, author = {los Roberto Junior Mingoto}, title = {A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2006}, issn = {0195-623X}, pages = {15}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2006.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors SN - 0195-623X SP EP A1 - los Roberto Junior Mingoto, PY - 2006 KW - null VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

los Roberto Junior Mingoto, University of Campinas, Brasil

In this work some Multi-Valued Logic (MVL) blocks are initially presented and they will be used to the final building of a Quaternary half-adder. A circuit equivalent to an Exclusive-OR binary gate from the binary world but working for the quaternary world is performed. Also, other basic gates are necessary like the shifter circuit, equivalent to the Not gate of the binary world, and the switching block, a core for the circuits here presented. All the circuits are built with bipolar transistors operating in current-mode.

Citation:

los Roberto Junior Mingoto, "A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors," ismvl, pp.15, 36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006

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