High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit

May 22-May 24

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http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.12

38th International Symposium on Multi ...

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	Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu, "High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit," Multiple-Valued Logic, IEEE International Symposium on, pp. 70-75, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008.

	BibTex	x
	@article{ 10.1109/ISMVL.2008.12, author = {Tasuku Nagai and Naoya Onizawa and Takahiro Hanyu}, title = {High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit}, journal ={Multiple-Valued Logic, IEEE International Symposium on}, volume = {0}, year = {2008}, issn = {0195-623X}, pages = {70-75}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2008.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Multiple-Valued Logic, IEEE International Symposium on TI - High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit SN - 0195-623X SP70 EP75 A1 - Tasuku Nagai, A1 - Naoya Onizawa, A1 - Takahiro Hanyu, PY - 2008 KW - Static timing analysis KW - Verilog-AMS KW - Look-up table VL - 0 JA - Multiple-Valued Logic, IEEE International Symposium on ER -

Tasuku Nagai

Naoya Onizawa

Takahiro Hanyu

A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

Index Terms:

Static timing analysis, Verilog-AMS, Look-up table

Citation:

Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu, "High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit," ismvl, pp.70-75, 38th International Symposium on Multiple Valued Logic (ismvl 2008), 2008

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