loading...
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
San Jose, California March 21-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.12Sixth International Symposium on Qual ...
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Animesh Datta, Purdue University
Swarup Bhunia, Purdue University
Nilanjan Banerjee, Purdue University
Kaushik Roy, Purdue University
We propose an adaptive scalable architecture suitable for performing real-time algorithm-specific tasks. The architecture is based on Globally Asynchronous and Locally Synchronous (GALS) design paradigm. We demonstrate that for different real-time commercial applications with algorithm-specific jobs like online transaction processing, Fourier transform etc., the proposed architecture allows dynamic load-balancing and adaptive inter-task voltage scaling. The architecture can also detect process-shifts for the individual processing units and determine their appropriate operating conditions. Simulation results for two representative applications show that for a random job distribution, we obtain up to 67% improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.
Citation:
Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy, "A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks," isqed, pp.358-363, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
Usage of this product signifies your acceptance of the Terms of Use.