C. K. Tang, University of Arkansas, Fayetteville, AR
P. K. Lala, University of Arkansas, Fayetteville, AR
A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.
Citation:
C. K. Tang, P. K. Lala, J. P. Parkerson, "A Technique for Designing Totally Self-Checking Domino Logic Circuits," isqed, pp.128-132, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005