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A Technique for Designing Totally Self-Checking Domino Logic Circuits
San Jose, California March 21-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.14Sixth International Symposium on Qual ...
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C. K. Tang, University of Arkansas, Fayetteville, AR
P. K. Lala, University of Arkansas, Fayetteville, AR
J. P. Parkerson, University of Arkansas, Fayetteville, AR
A scheme for concurrent self-checking domino logic circuit is proposed. The self-checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the self-checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.
Citation:
C. K. Tang, P. K. Lala, J. P. Parkerson, "A Technique for Designing Totally Self-Checking Domino Logic Circuits," isqed, pp.128-132, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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