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Early Assessment of Leakage Power for System Level Design
San Jose, California March 21-March 23
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.50Sixth International Symposium on Qual ...
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C. Talarico, University of Arizona, Tucson, AZ
B. Pillilli, University of Arizona, Tucson, AZ
K. L. Vakati, University of Arizona, Tucson, AZ
J. M. Wang, University of Arizona, Tucson, AZ
This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into accounts the simultaneous effect of threshold-voltage (Vt), oxide thickness (tox), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15X faster.
Citation:
C. Talarico, B. Pillilli, K. L. Vakati, J. M. Wang, "Early Assessment of Leakage Power for System Level Design," isqed, pp.133-136, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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