A low input, low-power dissipation CMOS ADC

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http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.11

7th International Symposium on Qualit ...

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	ASCII Text	x
	Biye Wang, Lili He, Morris Jones, "A low input, low-power dissipation CMOS ADC," Quality Electronic Design, International Symposium on, pp. 383-386, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.

	BibTex	x
	@article{ 10.1109/ISQED.2006.11, author = {Biye Wang and Lili He and Morris Jones}, title = {A low input, low-power dissipation CMOS ADC}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2523-7}, pages = {383-386}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A low input, low-power dissipation CMOS ADC SN - 0-7695-2523-7 SP383 EP386 A1 - Biye Wang, A1 - Lili He, A1 - Morris Jones, PY - 2006 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Biye Wang, San Jose State University

Lili He, San Jose State University

Morris Jones, San Jose State University

This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm ? 0.795 mm with TSMC025..m CMOS technology.

Citation:

Biye Wang, Lili He, Morris Jones, "A low input, low-power dissipation CMOS ADC," isqed, pp.383-386, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006

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