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Yield Enhancement Methodology for CMOS Standard Cells
San Jose, California March 27-March 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.1477th International Symposium on Qualit ...
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Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson, "Yield Enhancement Methodology for CMOS Standard Cells," Quality Electronic Design, International Symposium on, pp. 497-502, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISQED.2006.147,
author = {Arnaud Epinat and N. Vijayaraghavan and Matthieu Sautier and Olivier Callen and Sebastien Fabre and Ryan Ross and Paul Simon and Robin Wilson},
title = {Yield Enhancement Methodology for CMOS Standard Cells},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2523-7},
pages = {497-502},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.147},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Yield Enhancement Methodology for CMOS Standard Cells
SN - 0-7695-2523-7
SP497
EP502
A1 - Arnaud Epinat,
A1 - N. Vijayaraghavan,
A1 - Matthieu Sautier,
A1 - Olivier Callen,
A1 - Sebastien Fabre,
A1 - Ryan Ross,
A1 - Paul Simon,
A1 - Robin Wilson,
PY - 2006
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Arnaud Epinat, STMicroelectronics
N. Vijayaraghavan, STMicroelectronics
Matthieu Sautier, STMicroelectronics
Olivier Callen, STMicroelectronics
Sebastien Fabre, Philips Semiconductors
Ryan Ross, Freescale Semiconductor - Crolles2 Alliance Crolles, France
Paul Simon, Philips Semiconductors
Robin Wilson, STMicroelectronics
In order to maximize the yield of random logic in today?s advanced Deep Sub-Micron CMOS technologies we have developed a complete yield enhancement methodology for Cmos standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper will explain the methodology and demonstrate the results and benefits of this work through illustrated examples.
Citation:
Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson, "Yield Enhancement Methodology for CMOS Standard Cells," isqed, pp.497-502, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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