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Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching
San Jose, California March 27-March 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.577th International Symposium on Qualit ...
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Taeyong Je, Yungseon Eo, "Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching," Quality Electronic Design, International Symposium on, pp. 419-424, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISQED.2006.57,
author = {Taeyong Je and Yungseon Eo},
title = {Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2523-7},
pages = {419-424},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.57},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching
SN - 0-7695-2523-7
SP419
EP424
A1 - Taeyong Je,
A1 - Yungseon Eo,
PY - 2006
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Taeyong Je, Hanynag Univ., Ansan, Kyunggi-do, Korea
Yungseon Eo, Hanynag Univ., Ansan, Kyunggi-do, Korea
A new signal integrity verification method of integrated circuit interconnects with asynchronous circuit switching is presented. A ramp input is modeled with delayed step inputs. Then signal transient variations due to asynchronous input signal switching are accurately as well as efficiently determined by using Traveling-wavebased Waveform Approximation (TWA) technique. It is shown that using 90nm technology, the signal timing and crosstalk of multi-coupled lines with asynchronous switching inputs have an excellent agreement with SPICE simulation but its computation time is several thousand times faster than that of SPICE simulation using generic segment-based RLC circuit model.
Citation:
Taeyong Je, Yungseon Eo, "Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching," isqed, pp.419-424, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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