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A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor
San Jose, California March 27-March 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.77th International Symposium on Qualit ...
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Y. S. Chauhan, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
C. Anghel, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
F. Krummenacher, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
R. Gillon, AMI Semiconductor, Belgium
A. Baguenier, 3Cadence Design Systems, France
A Modeling strategy for High Voltage VDMOS transistors based on the intrinsic drain voltage and the use of EKV MOSFET model as a core for the intrinsic MOS channel is presented. The proposed charge based model correctly reproduces the special effects of high voltage devices like the quasi saturation, impact ionization and self heating. The accuracy of the model is better than 5% for DC I-V and g-V characteristics. We also report the accurate simulation of the intrinsic drain voltage, VK, which represents the basis of the AC model. The unique peaks on Cgs and Cgd characteristics peculiar to high voltage devices are accurately simulated by this charge based model. It is demonstrated that this model provides excellent trade-off between speed, convergence and accuracy, being suitable for circuit simulation in any operation regime of HV MOSFETs including all special effects of these devices.
Citation:
Y. S. Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, "A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor," isqed, pp.109-114, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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