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Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
San Jose, California March 27-March 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.977th International Symposium on Qualit ...
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Minh Q. Do, Mindaugas Dra?zd?ziulis, Per Larsson-Edefors, Lars Bengtsson, "Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration," Quality Electronic Design, International Symposium on, pp. 557-563, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006.
 
 
BibTex
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@article{ 10.1109/ISQED.2006.97,
author = {Minh Q. Do and Mindaugas Dra?zd?ziulis and Per Larsson-Edefors and Lars Bengtsson},
title = {Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2006},
isbn = {0-7695-2523-7},
pages = {557-563},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.97},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
SN - 0-7695-2523-7
SP557
EP563
A1 - Minh Q. Do,
A1 - Mindaugas Dra?zd?ziulis,
A1 - Per Larsson-Edefors,
A1 - Lars Bengtsson,
PY - 2006
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Minh Q. Do, Chalmers University of Technology, Sweden
Mindaugas Dra?zd?ziulis, Chalmers University of Technology, Sweden
Per Larsson-Edefors, Chalmers University of Technology, Sweden
Lars Bengtsson, Chalmers University of Technology, Sweden
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circuit-simulation backend used to obtain static leakage power values of all basic memory components. The method is flexible in that memory size is an arbitrary parameter. In a comparison to circuit-level simulations (Hspice) of complete 2 KBytes and 8 KBytes 6T-SRAM memories implemented both in 0.13-?m and 65-nm (BPTM) bulk CMOS processes, the proposed method shows a high accuracy in estimating leakage power.
Citation:
Minh Q. Do, Mindaugas Dra?zd?ziulis, Per Larsson-Edefors, Lars Bengtsson, "Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration," isqed, pp.557-563, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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