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SUB 45nm Low Power Design Challenges
San Jose, California March 26-March 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.1528th International Symposium on Qualit ...
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James W. Tschanz, "SUB 45nm Low Power Design Challenges," Quality Electronic Design, International Symposium on, pp. 4, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.
 
 
BibTex
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@article{ 10.1109/ISQED.2007.152,
author = {James W. Tschanz},
title = {SUB 45nm Low Power Design Challenges},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2795-7},
pages = {4},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.152},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - SUB 45nm Low Power Design Challenges
SN - 0-7695-2795-7
SP
EP
A1 - James W. Tschanz,
PY - 2007
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
The ever-increasing use of mobile devices and the constant desire for energy efficiency and long battery life have made low power design more important than ever. At the same time, continued technology scaling results in more devices per die, higher leakage current and power densities, and increased process variations.
Citation:
James W. Tschanz, "SUB 45nm Low Power Design Challenges," isqed, pp.4, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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