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Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
San Jose, California March 26-March 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.378th International Symposium on Qualit ...
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Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun, "Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability," Quality Electronic Design, International Symposium on, pp. 53-58, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.
 
 
BibTex
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@article{ 10.1109/ISQED.2007.37,
author = {Benoit Dubois and Jean-Baptiste Kammerer and Luc Hebrard and Francis Braun},
title = {Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2795-7},
pages = {53-58},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.37},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
SN - 0-7695-2795-7
SP53
EP58
A1 - Benoit Dubois,
A1 - Jean-Baptiste Kammerer,
A1 - Luc Hebrard,
A1 - Francis Braun,
PY - 2007
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Benoit Dubois, Institut d'Electronique du Solide et des Systemes, France
Jean-Baptiste Kammerer, Institut d'Electronique du Solide et des Systemes, France
Luc Hebrard, Institut d'Electronique du Solide et des Systemes, France
Francis Braun, Institut d'Electronique du Solide et des Systemes, France
A CMOS transistor ageing analytical model is presented and the procedure that allows to extract its parameters is proposed in this paper. By using a simple example, we show how such a model can be used to forecast the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the designer to choose and/or modify a circuit in order to minimize the hot-carrier induced degradations. Simulation results compared to the analytical study are also shown.
Citation:
Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun, "Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability," isqed, pp.53-58, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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