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Compact Modeling of a PD SOI MESFET for Wide Temperature Designs
San Jose, California March 26-March 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.498th International Symposium on Qualit ...
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Asha Balijepalli, Arizona State University, USA
Joseph Ervin, Arizona State University, USA
Yu Cao, Arizona State University, USA
Trevor Thornton, Arizona State University, USA
A compact model for the partially-depleted (PD) silicon-on- insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. The device has been fabricated using a standard CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried-oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180??C to 150??C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint??s Own Model (TOM3) MESFET model. A measurement-based approach is used to develop a 4-terminal device model. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also propose a wide-temperature compensation technique by source-voltage modulation.
Citation:
Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton, "Compact Modeling of a PD SOI MESFET for Wide Temperature Designs," isqed, pp.133-138, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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