In this paper the robustness of CML based phase detectors is analyzed with respect to the scaling of CMOS processes. Phase detectors are an important part of CDR circuits, which enable high-speed serial data links. As CDR circuits are integrated into monolithic CMOS ICs, their robustness becomes critically important. Three phase detectors are analyzed over corners in three standard CMOS processes: 180nm, 130nm and 90nm. The results of the simulations show that the total variation of the static phase offset increases with scaling for all phase detectors. The presence of a static phase offset is mathematically shown to negatively affect the BER of a CDR circuit. The analysis shows that the DFF binary phase detector has an advantage in terms of robustness however it has performance limitations. Both the Alexander and Hogge phase detector experience significant and increasing variations in static phase offset as the technology scales.