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Cross Layer Error Exploitation for Aggressive Voltage Scaling
San Jose, California March 26-March 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.538th International Symposium on Qualit ...
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Amin Khajeh Djahromi, UC Irvine, USA
Ahmed M. Eltawil, UC Irvine, USA
Fadi J. Kurdahi, UC Irvine, USA
Rouwaida Kanj, IBM Austin Research Labs, USA
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem.
Citation:
Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj, "Cross Layer Error Exploitation for Aggressive Voltage Scaling," isqed, pp.192-197, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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