Design-for-Manufacture for Multi Gate Oxide CMOS Process

San Jose, California March 26-March 28

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.58

8th International Symposium on Qualit ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Qi Lin Articles by Mei Ma Articles by Tony Vo Articles by Jenny Fan Articles by Xin Wu Articles by Richard Li Articles by Xiao-Yu Li

	ASCII Text	x
	Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li, "Design-for-Manufacture for Multi Gate Oxide CMOS Process," Quality Electronic Design, International Symposium on, pp. 339-343, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.

	BibTex	x
	@article{ 10.1109/ISQED.2007.58, author = {Qi Lin and Mei Ma and Tony Vo and Jenny Fan and Xin Wu and Richard Li and Xiao-Yu Li}, title = {Design-for-Manufacture for Multi Gate Oxide CMOS Process}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2795-7}, pages = {339-343}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.58}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Design-for-Manufacture for Multi Gate Oxide CMOS Process SN - 0-7695-2795-7 SP339 EP343 A1 - Qi Lin, A1 - Mei Ma, A1 - Tony Vo, A1 - Jenny Fan, A1 - Xin Wu, A1 - Richard Li, A1 - Xiao-Yu Li, PY - 2007 KW - DFM KW - FPGA KW - multi gate oxide KW - layout KW - yield. VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Qi Lin, Xilinx Inc., USA

Mei Ma, Xilinx Inc., USA

Tony Vo, Xilinx Inc., USA

Jenny Fan, Xilinx Inc., USA

Xin Wu, Xilinx Inc., USA

Richard Li, Xilinx Inc., USA

Xiao-Yu Li, Xilinx Inc., USA

Most of DFM emphasis has been placed on those so called "lithography critical layers" like diffusion, poly, contact and metal layers. However, "non-lithography-critical layers" impact on the manufacture and the yield has not been investigated well. This paper addresses the DFM issue for one of "non-lithography-critical layers", i.e. thick gate oxide layout in dual oxide product, which in this case impacts the product yield significantly. In this paper, a yield loss in a dual oxide FPGA product is analyzed, and the root cause is demonstrated and finally the DFM approaches for gate oxide design and layout are proposed.

Index Terms:

DFM, FPGA, multi gate oxide, layout, yield.

Citation:

Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li, "Design-for-Manufacture for Multi Gate Oxide CMOS Process," isqed, pp.339-343, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.