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A 8b 10Ms/s Low Power Pipelined A/D Converter
San Jose, California March 26-March 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.78th International Symposium on Qualit ...
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Bi Yuan, Yi Zhang, Lili He, "A 8b 10Ms/s Low Power Pipelined A/D Converter," Quality Electronic Design, International Symposium on, pp. 225-228, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007.
 
 
BibTex
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@article{ 10.1109/ISQED.2007.7,
author = {Bi Yuan and Yi Zhang and Lili He},
title = {A 8b 10Ms/s Low Power Pipelined A/D Converter},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2007},
isbn = {0-7695-2795-7},
pages = {225-228},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2007.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - A 8b 10Ms/s Low Power Pipelined A/D Converter
SN - 0-7695-2795-7
SP225
EP228
A1 - Bi Yuan,
A1 - Yi Zhang,
A1 - Lili He,
PY - 2007
KW - null
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
Bi Yuan, San Jose State University, USA
Yi Zhang, San Jose State University, USA
Lili He, San Jose State University, USA
This paper describes an 8-bit, 10 MSamples/second analog to digital converter, with 2V fully differential input range, which is implemented in TSMC 0.25?m CMOS technology. It achieves low power dissipation of 25mW, and the chip area is 0.56mm2. Measured performance yields a very good VTC curve and a sine wave fitting curve for 200KHz input at 10Msample/s, DNL testing of -0.2LSB~0.75LSB; INL testing of -0.2LSB~0.65LSB, 44.62dB of SNDR (signal to noise plus distortion ratio) and ENOB of 7.12 bits.
Citation:
Bi Yuan, Yi Zhang, Lili He, "A 8b 10Ms/s Low Power Pipelined A/D Converter," isqed, pp.225-228, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
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