Architecting for Physical Verification Performance and Scaling

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http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.109

9th International Symposium on Qualit ...

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	ASCII Text	x
	John Ferguson, Robert Todd, "Architecting for Physical Verification Performance and Scaling," Quality Electronic Design, International Symposium on, pp. 283-288, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.

	BibTex	x
	@article{ 10.1109/ISQED.2008.109, author = {John Ferguson and Robert Todd}, title = {Architecting for Physical Verification Performance and Scaling}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3117-5}, pages = {283-288}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.109}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Architecting for Physical Verification Performance and Scaling SN - 978-0-7695-3117-5 SP283 EP288 A1 - John Ferguson, A1 - Robert Todd, PY - 2008 KW - resource optimization KW - scaling KW - physical verification performance KW - scaling comparisons KW - turnaround time reduction VL - 0 JA - Quality Electronic Design, International Symposium on ER -

John Ferguson

Robert Todd

The primary goal when using physical verificationtools is to achieve the best performance at the lowestcost, both in resources and time. Physical verificationtools rely on multiple enabling technologies tocontribute to runtime and turnaround time reduction.Using differing combinations of architecture andscaling, this paper compares and contrasts threephysical verification approaches to determine thecombination of factors most likely to produce thedesired results in a production environment.

Index Terms:

resource optimization, scaling, physical verification performance, scaling comparisons, turnaround time reduction

Citation:

John Ferguson, Robert Todd, "Architecting for Physical Verification Performance and Scaling," isqed, pp.283-288, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008

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