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Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
March 17-March 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.1689th International Symposium on Qualit ...
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Tiago Muller Gil Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques, Renato Perez Ribas, Andre Inacio Reis, "Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering," Quality Electronic Design, International Symposium on, pp. 47-52, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.
 
 
BibTex
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@article{ 10.1109/ISQED.2008.168,
author = {Tiago Muller Gil Cardoso and Leomar Soares da Rosa Jr. and Felipe de Souza Marques and Renato Perez Ribas and Andre Inacio Reis},
title = {Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3117-5},
pages = {47-52},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.168},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
SN - 978-0-7695-3117-5
SP47
EP52
A1 - Tiago Muller Gil Cardoso,
A1 - Leomar Soares da Rosa Jr.,
A1 - Felipe de Souza Marques,
A1 - Renato Perez Ribas,
A1 - Andre Inacio Reis,
PY - 2008
KW - Transistor networks
KW - logic synthesis
KW - BDDs
KW - Logical effort
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.
Index Terms:
Transistor networks, logic synthesis, BDDs, Logical effort
Citation:
Tiago Muller Gil Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques, Renato Perez Ribas, Andre Inacio Reis, "Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering," isqed, pp.47-52, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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