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Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces
March 17-March 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.259th International Symposium on Qualit ...
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Characteristics of the on-chip power supply noise in a 6.4Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4Gbps are observed in time and frequency domain.
Index Terms:
I/O interface, supply noise
Citation:
Hai Lan, Ralf Schmitt, Chuck Yuan, "Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces," isqed, pp.670-675, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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