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On Chip Jitter Measurement through a High Accuracy TDC
March 17-March 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.689th International Symposium on Qualit ...
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Akhil Garg, Prashant Dubey, "On Chip Jitter Measurement through a High Accuracy TDC," Quality Electronic Design, International Symposium on, pp. 844-847, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.
 
 
BibTex
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@article{ 10.1109/ISQED.2008.68,
author = {Akhil Garg and Prashant Dubey},
title = {On Chip Jitter Measurement through a High Accuracy TDC},
journal ={Quality Electronic Design, International Symposium on},
volume = {0},
year = {2008},
isbn = {978-0-7695-3117-5},
pages = {844-847},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.68},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Quality Electronic Design, International Symposium on
TI - On Chip Jitter Measurement through a High Accuracy TDC
SN - 978-0-7695-3117-5
SP844
EP847
A1 - Akhil Garg,
A1 - Prashant Dubey,
PY - 2008
KW - Jitter Measurement
KW - PLL Test
VL - 0
JA - Quality Electronic Design, International Symposium on
ER -
 
In High speed applications, ratio of total jitter to clock period is critical. It necessitates accurate measurement of Jitter. In this paper we describe an on-chip methodology to measure jitter in time domain, with resolutions up to 0.1ps.
Index Terms:
Jitter Measurement, PLL Test
Citation:
Akhil Garg, Prashant Dubey, "On Chip Jitter Measurement through a High Accuracy TDC," isqed, pp.844-847, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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