A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS

March 17-March 19

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http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.81

9th International Symposium on Qualit ...

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	ASCII Text	x
	Mark Lysinger, Francois Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell, "A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS," Quality Electronic Design, International Symposium on, pp. 23-29, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008.

	BibTex	x
	@article{ 10.1109/ISQED.2008.81, author = {Mark Lysinger and Francois Jacquet and Mehdi Zamanian and David McClure and Philippe Roche and Naren Sahoo and John Russell}, title = {A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3117-5}, pages = {23-29}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.81}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS SN - 978-0-7695-3117-5 SP23 EP29 A1 - Mark Lysinger, A1 - Francois Jacquet, A1 - Mehdi Zamanian, A1 - David McClure, A1 - Philippe Roche, A1 - Naren Sahoo, A1 - John Russell, PY - 2008 KW - Rad Hard VL - 0 JA - Quality Electronic Design, International Symposium on ER -

An eight megabit Rad Hard SRAM, implemented in 130nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600nA.

Index Terms:

Rad Hard

Citation:

Mark Lysinger, Francois Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell, "A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS," isqed, pp.23-29, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008

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